82NM10 Datasheet, PDF (269/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Chipset Configuration Registers
Bit
15
14
13:8
7:0
Description
Reject Snoop Transactions (RTS) — RO. This VC must be able to take snoopable
transactions.
Advanced Packet Switching (APS) — RO. This VC is capable of all transactions,
not just advanced packet switching transactions.
Reserved
Port Arbitration Capability (PAC) — RO. This field indicates that this VC uses fixed
port arbitration.
10.1.7
V0CTL—Virtual Channel 0 Resource Control Register
Offset Address: 0014–0017h
Default Value: 800000FFh
Attribute:
Size:
R/W, RO
32-bit
Bit
Description
31
30:27
26:24
23:20
19:17
16
15:8
7:1
0
Virtual Channel Enable (EN) — RO. Always set to 1. VC0 is always enabled and
cannot be disabled.
Reserved
Virtual Channel Identifier (ID) — RO. This field indicates the ID to use for this
virtual channel.
Reserved
Port Arbitration Select (PAS) — R/W. This field indicates which port table is being
programmed. The root complex takes no action on this setting since the arbitration is
fixed and there is no arbitration table.
Load Port Arbitration Table (LAT) — RO. The root complex does not implement
an arbitration table for this virtual channel.
Reserved
Transaction Class / Virtual Channel Map (TVM) — R/W. This field indicates
which transaction classes are mapped to this virtual channel. When a bit is set, this
transaction class is mapped to the virtual channel.
Reserved
10.1.8
V0STS—Virtual Channel 0 Resource Status Register
Offset Address: 001A–001Bh
Default Value: 0000h
Attribute:
Size:
RO
16-bit
Bit
Description
15:02
1
0
Reserved
VC Negotiation Pending (NP) — RO. When set, this bit indicates the virtual
channel is still being negotiated with ingress ports.
Port Arbitration Tables Status (ATS) — RO. There is no port arbitration table for
this VC, so this bit is reserved at 0.
Datasheet
269