82NM10 Datasheet, PDF (48/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Signal Description
Table 2-8. PCI Interface Signals (Sheet 2 of 3)
Name
TRDY#
STOP#
PAR
PERR#
REQ[2:1]
GNT[2:1]#
PCICLK
PCIRST#
Type
Description
Target Ready: TRDY# indicates chipset's ability as a target to
complete the current data phase of the transaction. TRDY# is used in
conjunction with IRDY#. A data phase is completed when both TRDY#
and IRDY# are sampled asserted. During a read, TRDYB indicates that
I/O
chipset, as a target, has placed valid data on AD[31:0]. During a write,
TRDY# indicates chipset, as a target is prepared to latch data. TRDY#
is an input to chipset when chipset is the initiator and an output from
chipset when chipset is a target. TRDY# is tri-stated from the leading
edge of PLTRST#. TRDY# remains tri-stated by chipset until driven by a
target.
Stop: STOP# indicates that chipset, as a target, is requesting the
I/O
initiator to stop the current transaction. STOP# causes chipset, as an
initiator, to stop the current transaction. STOPB is an output when
chipset is a target and an input when chipset is an initiator.
Calculated/Checked Parity: PAR uses “even” parity calculated on 36
bits, AD[31:0] plus C/BE[3:0]B. “Even” parity means that chipset
counts the number of 1s within the 36 bits plus PAR and the sum is
always even. chipset calculates PAR on 36 bits regardless of the valid
byte enables. chipset generates PAR for address and data phases and
only ensures PAR to be valid one PCI clock after the corresponding
address or data phase. chipset drives and tri-states PAR identically to
I/O the AD[31:0] lines except that chipset delays PAR by exactly one PCI
clock. PAR is an output during the address phase (delayed one clock)
for all chipset initiated transactions. PAR is an output during the data
phase (delayed one clock) when chipset is the initiator of a PCI write
transaction, and when it is the target of a read transaction. chipset
checks parity when it is the target of a PCI write transaction. If a parity
error is detected, chipset will set the appropriate internal status bits,
and has the option to generate an NMIB or SMIB.
Parity Error: An external PCI device drives PERRB when it receives
data that has a parity error. chipset drives PERRB when it detects a
I/O parity error. chipset can either generate an NMIB or SMIB upon
detecting a parity error (either detected internally or reported via the
PERR# signal).
I PCI Requests: chipset supports up to 2 masters on the PCI bus.
PCI Grants: chipset supports up to 2 masters on the PCI bus.
O _{Pull-up resistors are not required on these signals. If pull-ups are used,}
they should be tied to the Vcc3_3 power rail.
I
PCI Clock: This is a 33 MHz clock. PCICLK provides timing for all
transactions on the PCI Bus.
PCI Reset: This is the Secondary PCI Bus reset signal. It is a logical
O
OR of the primary interface PLTRST# signal and the state of the
Secondary Bus Reset bit of the Bridge Control register (D30:F0:3Eh, bit
6).
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Datasheet