82NM10 Datasheet, PDF (437/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
Table 13-130.TCO I/O Register Address Map
TCOBASE
+ Offset
08h–09h
Mnemonic
TCO1_CNT
Register Name
TCO1 Control
0Ah–0Bh
0Ch–0Dh
0Eh
0Fh
10h
11h
12h–13h
14h–1Fh
TCO2_CNT
TCO2 Control
TCO_MESSAGE1, TCO Message 1 and 2
TCO_MESSAGE2
TCO_WDCNT Watchdog Control
—
Reserved
SW_IRQ_GEN Software IRQ Generation
—
Reserved
TCO_TMR
TCO Timer Initial Value
—
Reserved
Default
0000h
0008h
00h
00h
—
11h
—
0004h
—
Type
R/W,
R/W
(special),
R/WC
R/W
R/W
R/W
—
R/W
—
R/W
—
13.9.1
13.9.2
TCO_RLD—TCO Timer Reload and Current Value Register
I/O Address:
Default Value:
Lockable:
TCOBASE +00h
0000h
No
Attribute:
Size:
Power Well:
R/W
16-bit
Core
Bit
Description
15:10 Reserved
9:0 TCO Timer Value — R/W. Reading this register will return the current count of the TCO
timer. Writing any value to this register will reload the timer to prevent the timeout.
TCO_DAT_IN—TCO Data In Register
I/O Address:
Default Value:
Lockable:
TCOBASE +02h
00h
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Bit
Description
7:0 TCO Data In Value — R/W. This data register field is used for passing commands from
the OS to the SMI handler. Writes to this register will cause an SMI and set the
SW_TCO_SMI bit in the TCO1_STS register (D31:F0:04h).
Datasheet
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