82NM10 Datasheet, PDF (629/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI Express* Configuration Registers
Bit
Description
31:20 Memory Limit (ML) — R/W. These bits are compared with bits 31:20 of the incoming
address to determine the upper 1-MB aligned value of the range.
19:16 Reserved
15:4 Memory Base (MB) — R/W. These bits are compared with bits 31:20 of the incoming
address to determine the lower 1-MB aligned value of the range.
3:0 Reserved
19.1.16 PMBL—Prefetchable Memory Base and Limit Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 24h–27h
Default Value: 00010001h
Attribute:
Size:
R/W, RO
32 bits
Accesses that are within the ranges specified in this register will be sent to the device if
CMD.MSE (D28:F0/F1/F2/F3;04, bit 1) is set. Accesses from the device that are outside
the ranges specified will be forwarded to the backbone if CMD.BME (D28:F0/F1/F2/
F3;04, bit 2) is set. The comparison performed is:
PMBU32:PMB ≥ AD[63:32]:AD[31:20] ≤ PMLU32:PML.
Bit
Description
31:20 Prefetchable Memory Limit (PML) — R/W. These bits are compared with bits 31:20
of the incoming address to determine the upper 1-MB aligned value of the range.
19:16 64-bit Indicator (I64L) — RO. This field indicates support for 64-bit addressing
15:4 Prefetchable Memory Base (PMB) — R/W. These bits are compared with bits 31:20
of the incoming address to determine the lower 1-MB aligned value of the range.
3:0 64-bit Indicator (I64B) — RO. This field indicates support for 64-bit addressing
19.1.17 PMBU32—Prefetchable Memory Base Upper 32 Bits
Register (PCI Express—D28:F0/F1/F2/F3)
Address Offset: 28h–2Bh
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bit
Description
31:0 Prefetchable Memory Base Upper Portion (PMBU) — R/W. This field contains the
Upper 32-bits of the prefetchable address base.
19.1.18 PMLU32—Prefetchable Memory Limit Upper 32 Bits
Register (PCI Express—D28:F0/F1/F2/F3)
Address Offset: 2Ch–2Fh
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bit
Description
31:0 Prefetchable Memory Limit Upper Portion (PMLU) — R/W. This field contains the
Upper 32-bits of the prefetchable address limit.
Datasheet
629