82NM10 Datasheet, PDF (455/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

UHCI Controllers Registers
14.1.14 INT_LN—Interrupt Line Register
(USB—D29:F0/F1/F2/F3)
Address Offset:
3ChAttribute:R/W
Default Value:
00hSize:8 bits
Bit
Description
7:0 Interrupt Line (INT_LN) — RO. This data is not used by the Chipset. It is to
communicate to software the interrupt line that the interrupt pin is connected to.
14.1.15 INT_PN—Interrupt Pin Register
(USB—D29:F0/F1/F2/F3)
Address Offset:
3DhAttribute:RO
Default Value:
Function 0: See DescriptionSize:8 bits
Function 1: See Description
Function 2: See Description
Function 3: See Description
Bit
Description
7:0 Interrupt Line (INT_LN) — RO. This value tells the software which interrupt pin each
USB host controller uses. The upper 4 bits are hardwired to 0000b; the lower 4 bits are
determine by the Interrupt Pin default values that are programmed in the memory-
mapped configuration space as follows:
Function 0
D29IP.U0P (Chipset Config Registers:Offset 3108:bits 3:0)
Function 1
D29IP.U1P (Chipset Config Registers:Offset 3108:bits 7:4)
Function 2
D29IP.U2P (Chipset Config Registers:Offset 3108:bits 11:8)
Function 3
D29IP.U3P (Chipset Config Registers:Offset 3108:bits 15:12)
NOTE: This does not determine the mapping to the PIRQ pins.
14.1.16 USB_RELNUM—Serial Bus Release Number Register
(USB—D29:F0/F1/F2/F3)
Address Offset:
60hAttribute:RO
Default Value:
10hSize:8 bits
Bit
Description
7:0 Serial Bus Release Number — RO.
10h = USB controller supports the USB Specification, Release 1.0.
Datasheet
455