82NM10 Datasheet, PDF (158/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
5.14.12 Clock Generators
The clock generator is expected to provide the frequencies shown in Table 5-67.
Table 5-67.Chipset Clock Inputs
Clock
Domain
Frequency Source
Usage
SATA_CLK
DMI_CLK
PCICLK
CLK48
CLK14
LAN_CLK
100 MHz Main Clock Used by SATA controller. Stopped in S3 ~ S5 based
Differential ^{Generator on SLP_S3# assertion.}
100 MHz Main Clock Used by DMI and PCI Express*. Stopped in S3 ~ S5
Differential ^{Generator based on SLP_S3# assertion.}
33 MHz
Main Clock
Generator
Nettop Only: Free-running PCI Clock to Chipset.
Stopped in S3 ~ S5 based on SLP_S3# assertion.
Netbook Only: Free-running (not affected by
STP_PCI# PCI Clock to Chipset. This is not the
system PCI clock. This clock must keep running in
S0 while the system PCI clock may stop based on
CLKRUN# protocol. Stopped in S3 ~ S5 based on
SLP_S3# assertion.
48.000
MHz
Main Clock Used by USB controllers and Intel HD Audio
Generator controller. Stopped in S3 ~ S5 based on SLP_S3#
assertion.
14.318
MHz
Main Clock Used by ACPI timers. Stopped in S3 ~ S5 based on
Generator SLP_S3# assertion.
0.8 to
50 MHz
LAN
LAN Connect Interface. Control policy is determined
Connect by the clock source.
5.14.12.1 Clock Control Signals from Chipset to Clock
Synthesizer (Netbook Only)
The clock generator is assumed to have a direct connection from the following Chipset
signals:
• STP_CPU#: Stops processor clocks in C3 and C4 states
• STP_PCI#: Stops system PCI clocks (not Chipset free-running 33 MHz clock) due to
CLKRUN# protocol
• SLP_S3#: Expected to drive clock chip PWRDOWN (through inverter), to stop
clocks in S3_HOT and on the way to S3_COLD to S5.
158
Datasheet