82NM10 Datasheet, PDF (368/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
13.1.25 GEN4_DEC—LPC I/F Generic Decode Range 4Register
(LPC I/F—D31:F0)
Offset Address: 90h – 93h
Default Value: 00000000h
Attribute:
Size:
Power Well:
R/W
32 bit
Core
Bit
Description
31:24 Reserved
23:18
Generic I/O Decode Range Address[7:2] Mask: A ‘1’ in any bit position indicates
that any value in the corresponding address bit in a received cycle will be treated as a
match. The corresponding bit in the Address field, below, is ignored. The mask is only
provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to
256 bytes in size.
17:16 Reserved
15:2 Generic I/O Decode Range 4Base Address (GEN4_BASE) — R/W.
NOTE: The Chipset does not provide decode down to the word or byte level.
1 Reserved
0 Generic Decode Range 4Enable (GEN4_EN) — R/W.
0 = Disable.
1 = Enable the GEN4 I/O range to be forwarded to the LPC I/F
13.1.26 FWH_SEL1—Firmware Hub Select 1 Register
(LPC I/F—D31:F0)
Offset Address: D0h–D3h
Default Value: 00112233h
Attribute:
Size:
R/W, RO
32 bits
Bit
Description
31:28
FWH_F8_IDSEL — RO. IDSEL for two 512-KB Firmware Hub memory ranges and one
128-KB memory range. This field is fixed at 0000. The IDSEL programmed in this field
addresses the following memory ranges:
FFF8 0000h – FFFF FFFFh
FFB8 0000h – FFBF FFFFh
000E 0000h – 000F FFFFh
27:24
FWH_F0_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The
IDSEL programmed in this field addresses the following memory ranges:
FFF0 0000h – FFF7 FFFFh
FFB0 0000h – FFB7 FFFFh
23:20
FWH_E8_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The
IDSEL programmed in this field addresses the following memory ranges:
FFE8 0000h – FFEF FFFFh
FFA8 0000h – FFAF FFFFh
19:16
FWH_E0_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The
IDSEL programmed in this field addresses the following memory ranges:
FFE0 0000h – FFE7 FFFFh
FFA0 0000h – FFA7 FFFFh
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Datasheet