82NM10 Datasheet, PDF (413/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
13.8.2
APM I/O Decode
Table 13-128 shows the I/O registers associated with APM support. This register space
is enabled in the PCI Device 31: Function 0 space (APMDEC_EN), and cannot be moved
(fixed I/O location).
Table 13-128.APM Register Map
Address Mnemonic
Register Name
B2h
APM_CNT Advanced Power Management Control Port
B3h
APM_STS Advanced Power Management Status Port
Default
00h
00h
Type
R/W
R/W
13.8.2.1 APM_CNT—Advanced Power Management Control Port
Register
I/O Address:
Default Value:
Lockable:
Power Well:
B2h
00h
No
Core
Attribute:
Size:
Usage:
R/W
8-bit
Legacy Only
Bit
Description
7:0 Used to pass an APM command between the OS and the SMI handler. Writes to this
port not only store data in the APMC register, but also generates an SMI# when the
APMC_EN bit is set.
13.8.2.2 APM_STS—Advanced Power Management Status Port
Register
I/O Address:
Default Value:
Lockable:
Power Well:
B3h
00h
No
Core
Attribute:
Size:
Usage:
R/W
8-bit
Legacy Only
Bit
Description
7:0 Used to pass data between the OS and the SMI handler. Basically, this is a scratchpad
register and is not affected by any other register or function (other than a PCI reset).
13.8.3
Note:
Power Management I/O Registers
Table 13-129 shows the registers associated with ACPI and Legacy power management
support. These registers are enabled in the PCI Device 31: Function 0 space
(PM_IO_EN), and can be moved to any I/O location (128-byte aligned). The registers
are defined to support the ACPI 2.0 specification, and use the same bit names.
All reserved bits and registers will always return 0 when read, and will have no effect
when written.
Datasheet
413