82NM10 Datasheet, PDF (319/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LAN Controller Registers (B1:D8:F0)
11.2.9
Bit
Description
7:0 Early Receive Count — R/W. When some non-zero value x is programmed into this
register, the LAN controller will set the ER bit in the SCB Status Word Register and assert
INTA# when the byte count indicates that there are x qwords remaining to be received
in the current frame (based on the Type/Length field of the received frame). No Early
Receive interrupt will be generated if a value of 00h (the default value) is programmed
into this register.
FLOW_CNTL—Flow Control Register
(LAN Controller—B1:D8:F0)
Offset Address: 19h–1Ah
Default Value: 0000h
Attribute:
Size:
RO, R/W (special)
16 bits
Bit
Description
15:13 Reserved
12 FC Paused Low — RO.
0 = Cleared when the FC timer reaches 0, or a Pause frame is received.
1 = Set when the LAN controller receives a Pause Low command with a value greater
than 0.
11 FC Paused — RO.
0 = Cleared when the FC timer reaches 0.
1 = Set when the LAN controller receives a Pause command regardless of its cause
(FIFO reaching Flow Control Threshold, fetching a Receive Frame Descriptor with its
Flow Control Pause bit set, or software writing a 1 to the Xoff bit).
10 FC Full — RO.
0 = Cleared when the FC timer reaches 0.
1 = Set when the LAN controller sends a Pause command with a value greater than 0.
9 Xoff — R/W (special). This bit should only be used if the LAN controller is configured to
operate with IEEE frame-based flow control.
0 = This bit can only be cleared by writing a 1 to the Xon bit (bit 8 in this register).
1 = Writing a 1 to this bit forces the Xoff request to 1 and causes the LAN controller to
behave as if the FIFO extender is full. This bit will also be set to 1 when an Xoff
request due to an “RFD Xoff” bit.
Datasheet
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