82NM10 Datasheet, PDF (384/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
13.3.4
Bit
Description
7:6 Counter Selection. These bits select the counter for latching. If “11” is written, then
the write is interpreted as a read back command.
00 = Counter 0
01 = Counter 1
10 = Counter 2
5:4 Counter Latch Command.
00 = Selects the Counter Latch Command.
3:0 Reserved. Must be 0.
SBYTE_FMT—Interval Timer Status Byte Format Register
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Counter 0 = 40h,
Counter 1 = 41h,
Attribute:RO
Counter 2 = 42h
Size:8 bits per counter
Bits[6:0] undefined, Bit 7=0
Each counter's status byte can be read following a Read Back Command. If latch status
is chosen (bit 4=0, Read Back Command) as a read back option for a given counter, the
next read from the counter's Counter Access Ports Register (40h for counter 0, 41h for
counter 1, and 42h for counter 2) returns the status byte. The status byte returns the
following:
Bit
Description
7 Counter OUT Pin State — RO.
0 = OUT pin of the counter is also a 0
1 = OUT pin of the counter is also a 1
6 Count Register Status — RO. This bit indicates when the last count written to the
Count Register (CR) has been loaded into the counting element (CE). The exact time
this happens depends on the counter mode, but until the count is loaded into the
counting element (CE), the count value will be incorrect.
0 = Count has been transferred from CR to CE and is available for reading.
1 = Null Count. Count has not been transferred from CR to CE and is not yet available
for reading.
5:4 Read/Write Selection Status — RO. These bits reflect the read/write selection made
through bits[5:4] of the control register. The binary codes returned during the status
read match the codes used to program the counter read/write selection.
00 = Counter Latch Command
01 = Read/Write Least Significant Byte (LSB)
10 = Read/Write Most Significant Byte (MSB)
11 = Read/Write LSB then MSB
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