82NM10 Datasheet, PDF (394/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
Note:
at a later time. Note: Only bits 7:0 are actually used. Bits 31:8 are ignored by the
Chipset.
To provide for future expansion, the processor should always write a value of 0 to Bits
31:8.
13.5.5
13.5.6
Bit
Description
31:8 Reserved. To provide for future expansion, the processor should always write a value
of 0 to Bits 31:8.
7:0 Redirection Entry Clear — WO. When a write is issued to this register, the I/O APIC
will check this field, and compare it with the vector field for each entry in the I/O
Redirection Table. When a match is found, the Remote_IRR bit for that I/O Redirection
Entry will be cleared.
ID—Identification Register (LPC I/F—D31:F0)
Index Offset: 00h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
The APIC ID serves as a physical name of the APIC. The APIC bus arbitration ID for the
APIC is derived from its I/O APIC ID. This register is reset to 0 on power-up reset.
Bit
Description
31:28 Reserved
27:24 APIC ID — R/W. Software must program this value before using the APIC.
23:16 Reserved
15 Scratchpad Bit.
14:0 Reserved
VER—Version Register (LPC I/F—D31:F0)
Index Offset: 01h
Default Value: 00170020h
Attribute:
Size:
RO
32 bits
Each I/O APIC contains a hardwired Version Register that identifies different
implementation of APIC and their versions. The maximum redirection entry information
also is in this register, to let software know how many interrupt are supported by this
APIC.
Bit
Description
31:24 Reserved
23:16
Maximum Redirection Entries — RO. This field is the entry number (0 being the lowest
entry) of the highest entry in the redirection table. It is equal to the number of
interrupt input pins minus one and is in the range 0 through 239. In the Chipset this
field is hardwired to 17h to indicate 24 interrupts.
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Datasheet