82NM10 Datasheet, PDF (514/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
Bit
Description
11:8 Interface Power Management Transitions Allowed (IPM) — R/W. Indicates which
power states the Chipset is allowed to transition to:
Value
Description
0h
No interface restrictions
1h
Transitions to the PARTIAL state disabled
2h
Transitions to the SLUMBER state disabled
3h
Transitions to both PARTIAL and SLUMBER states disabled
All other values reserved
7:4 Speed Allowed (SPD) — R/W. Indicates the highest allowable speed of the interface.
This speed is limited by the CAP.ISS (ABAR+00h:bit 23:20) field.
Value
0h
1h
2h
Description
No speed negotiation restrictions
Limit speed negotiation to Generation 1 communication rate
Limit speed negotiation to Generation 2 communication rate
All other values reserved
Chipset Supports Generation 1 communication rates (1.5 Gb/sec) and Gen 2 rates (3.0
Gb/s).
3:0 Device Detection Initialization (DET) — R/W. Controls the chipset’s device
detection and interface initialization.
Value
0h
1h
4h
Description
No device detection or initialization action requested
Perform interface communication initialization sequence to
establish communication. This is functionally equivalent to a hard
reset and results in the interface being reset and communications
re-initialized
Disable the Serial ATA interface and put Phy in offline mode
All other values reserved.
When this field is written to a 1h, the Chipset initiates COMRESET and starts the
initialization process. When the initialization is complete, this field shall remain 1h until
set to another value by software.
This field may only be changed to 1h or 4h when PxCMD.ST is 0. Changing this field
while the Chipset is running results in undefined behavior.
15.3.2.12 PxSERR—Port [1:0] Serial ATA Error Register (D31:F2)
Address Offset: Port 0: ABAR + 130h
Port 1: ABAR + 1B0h
Attribute:
R/WC
Default Value: 00000000h
Size:
32 bits
514
Datasheet