82NM10 Datasheet, PDF (579/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Intel HD Audio Controller Registers (D27:F0)
18.1.17 INTLN—Interrupt Line Register
(Intel HD Audio Controller—D27:F0)
Address Offset: 3Ch
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:0 Interrupt Line (INT_LN) — R/W. This data is not used by the Chipset. It is used to
communicate to software the interrupt line that the interrupt pin is connected to.
18.1.18 INTPN—Interrupt Pin Register
(Intel HD Audio Controller—D27:F0)
Address Offset: 3Dh
Default Value: See Description
Attribute:
Size:
RO
8 bits
Bit
Description
7:4 Reserved.
3:0 Interrupt Pin — RO. This reflects the value of D27IP.ZIP (Chipset Config
Registers:Offset 3110h:
bits 3:0).
18.1.19 HDCTL—Intel HD Audio Control Register
(Intel HD Audio Controller—D27:F0)
Address Offset: 40h
Default Value: 00h
Attribute:
Size:
R/W, RO
8 bits
Bit
Description
7:4 Reserved.
3 BITCLK Detect Clear (CLKDETCLR) — R/W.
0 = lock detect circuit is operational and maybe enabled.
1 = Writing a 1 to this bit clears bit 1 (CLKDET#) in this register. CLKDET# bit remains
clear when this bit is set to 1.
NOTE: This bit is not affected by the D3_HOT to D0 transition.
2 BITCLK Detect Enable (CLKDETEN) — R/W.
0 = Latches the current state of bit 1 (CLKDET#) in this register
1 = Enables the clock detection circuit
NOTE: This bit is not affected by the D3_HOT to D0 transition.
Datasheet
579