82NM10 Datasheet, PDF (97/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
5.5
LPC Bridge (w/ System and Management
Functions) (D31:F0)
The LPC bridge function of Chipset resides in PCI Device 31:Function 0. In addition to
the LPC bridge function, D31:F0 contains other functional units including DMA,
Interrupt controllers, Timers, Power Management, System Management, GPIO, and
RTC. In this chapter, registers and functions associated with other functional units
(power management, GPIO, USB, IDE, etc.) are described in their respective sections.
5.5.1 LPC Interface
Chipset implements an LPC interface as described in the Low Pin Count Interface
Specification, Revision 1.1. The LPC interface to Chipset is shown in Figure 5-8. Note
that Chipset implements all of the signals that are shown as optional, but peripherals
are not required to do so.
Figure 5-8. LPC Interface Diagram
5.5.1.1
LPC Cycle Types
Chipset implements the following cycle types as described in Table 5-33
Table 5-33.LPC Cycle Types Supported
Cycle Type
I/O Read
I/O Write
DMA Read
DMA Write
Bus Master Read
Bus Master Write
Comment
1 byte only. Chipset breaks up 16- and 32-bit processor cycles into
multiple 8-bit transfers.
1 byte only. Chipset breaks up 16- and 32-bit processor cycles into
multiple 8-bit transfers.
Can be 1, or 2 bytes
Can be 1, or 2 bytes
Can be 1, 2, or 4 bytes. (See Note 1 below)
Can be 1, 2, or 4 bytes. (See Note 1 below)
NOTES:
1.
Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer
can be to any address. However, the 2-byte transfer must be word-aligned (i.e., with an
address where A0=0). A dword transfer must be dword-aligned (i.e., with an address
where A1 and A0 are both 0)
Datasheet
97