82NM10 Datasheet, PDF (348/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI-to-PCI Bridge Registers (D30:F0)
12.1.16 PMLU32—Prefetchable Memory Limit Upper 32 Bits
Register (PCI-PCI—D30:F0)
Offset Address: 2C–2Fh
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bit
Description
31:0 Prefetchable Memory Limit Upper Portion (PMLU) — R/W. Upper 32-bits of the
prefetchable address limit.
12.1.17 CAPP—Capability List Pointer Register (PCI-PCI—D30:F0)
Offset Address: 34h
Default Value: 50h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0 Capabilities Pointer (PTR) — RO. Indicates that the pointer for the first entry in the
capabilities list is at 50h in configuration space.
12.1.18 INTR—Interrupt Information Register (PCI-PCI—D30:F0)
Offset Address: 3Ch–3Dh
Default Value: 0000h
Attribute:
Size:
R/W, RO
16 bits
Bit
Description
15:8
7:0
Interrupt Pin (IPIN) — RO. The PCI bridge does not assert an interrupt.
Interrupt Line (ILINE) — R/W. Software written value to indicate which interrupt line
(vector) the interrupt is connected to. No hardware action is taken on this register.
Since the bridge does not generate an interrupt, BIOS should program this value to FFh
as per the PCI bridge specification.
12.1.19 BCTRL—Bridge Control Register (PCI-PCI—D30:F0)
Offset Address: 3Eh–3Fh
Default Value: 0000h
Attribute:
Size:
R/WC, RO
16 bits
Bit
Description
15:12 Reserved
11 Discard Timer SERR# Enable (DTE) — R/W. Controls the generation of SERR# on
the primary interface in response to the DTS bit being set:
0 = Do not generate SERR# on a secondary timer discard
1 = Generate SERR# in response to a secondary timer discard
10 Discard Timer Status (DTS) — R/WC. This bit is set to 1 when the secondary
discard timer (see the SDT bit below) expires for a delayed transaction in the hard
state.
348
Datasheet