82NM10 Datasheet, PDF (485/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
15.1.26 PID—PCI Power Management Capability Identification
Register (SATA–D31:F2)
Address Offset: 70h–71h
Default Value: XX01h
Attribute:
Size:
RO
16 bits
Bits
Description
15:8
7:0
Next Capability (NEXT) — RO.
00h — if SCC = 01h (IDE mode).
A8h — for all other values of SCC to point to the next capability structure.
This field is changed to 00h if the SCRD bit (D31:F2;Offset 94h bit-30) is set.
Capability ID (CID) — RO. Indicates that this pointer is a PCI power management.
15.1.27 PC—PCI Power Management Capabilities Register
(SATA–D31:F2)
Address Offset: 72h–73h
Default Value: 4002h
f
Attribute:
Size:
RO
16 bits
Bits
Description
15:11 PME Support (PME_SUP) — RO. Indicates PME# can be generated from the D3_HOT state
in the SATA host controller.
10 D2 Support (D2_SUP) — RO. Hardwired to 0. The D2 state is not supported
9 D1 Support (D1_SUP) — RO. Hardwired to 0. The D1 state is not supported
8:6 Auxiliary Current (AUX_CUR) — RO. PME# from D3COLD state is not supported,
therefore this field is 000b.
5 Device Specific Initialization (DSI) — RO. Hardwired to 0 to indicate that no device-
specific initialization is required.
4 Reserved
3 PME Clock (PME_CLK) — RO. Hardwired to 0 to indicate that PCI clock is not required to
generate PME#.
2:0 Version (VER) — RO. Hardwired to 010 to indicates support for Revision 1.1 of the PCI
Power Management Specification.
15.1.28 PMCS—PCI Power Management Control and Status
Register (SATA–D31:F2)
Address Offset: 74h–75h
Default Value: 0000h
Attribute:
Size:
RO, R/W, R/WC
16 bits
Bits
Description
15
14:9
PME Status (PMES) — R/WC. Bit is set when a PME event is to be requested, and if
this bit and PMEE is set, a PME# will be generated from the SATA controller.
Reserved
Datasheet
485