82NM10 Datasheet, PDF (393/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
Table 13-123.APIC Indirect Registers (LPC I/F—D31:F0)
Index
12–13
...
3E–3F
40–FF
Mnemonic
Register Name
REDIR_TBL1 Redirection Table 1
...
...
REDIR_TBL23 Redirection Table 23
—
Reserved
Size
64 bits
...
64 bits
—
Type
R/W, RO
...
R/W, RO
RO
13.5.2
.
13.5.3
13.5.4
Note:
IND—Index Register (LPC I/F—D31:F0)
Memory Address FEC0_0000h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
The Index Register will select which APIC indirect register to be manipulated by
software. The selector values for the indirect registers are listed in Table 13-123.
Software will program this register to select the desired APIC internal register
Bit
Description
7:0 APIC Index — R/W. This is an 8-bit pointer into the I/O APIC register table.
DAT—Data Register (LPC I/F—D31:F0)
Memory Address FEC0_0010h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
This is a 32-bit register specifying the data to be read or written to the register pointed
to by the Index register. This register can only be accessed in DWord quantities.
Bit
Description
7:0 APIC Data — R/W. This is a 32-bit register for the data to be read or written to the
APIC indirect register (Table 13-123) pointed to by the Index register (Memory Address
FEC0_0000h).
EOIR—EOI Register (LPC I/F—D31:F0)
Memory Address FEC0h_0040h
Default Value: N/A
Attribute:
Size:
WO
32 bits
The EOI register is present to provide a mechanism to maintain the level triggered
semantics for level-triggered interrupts issued on the parallel bus.
When a write is issued to this register, the I/O APIC will check the lower 8 bits written
to this register, and compare it with the vector field for each entry in the I/O
Redirection Table. When a match is found, the Remote_IRR bit (Index Offset 10h, bit
14) for that I/O Redirection Entry will be cleared.
If multiple I/O Redirection entries, for any reason, assign the same vector for more
than one interrupt input, each of those entries will have the Remote_IRR bit reset to 0.
The interrupt which was prematurely reset will not be lost because if its input remained
active when the Remote_IRR bit is cleared, the interrupt will be reissued and serviced
Datasheet
393