82NM10 Datasheet, PDF (146/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
Table 5-59.Causes of Wake Events
Cause
PCI_EXP_WAKE#
PCI_EXP PME
Message
SMBALERT#
SMBus Slave
Message
SMBus Host
Notify message
received
States Can
Wake From¹
How Enabled
S1–S5
PCI_EXP_WAKE bit³
S1
Must use the PCI Express* WAKE# pin rather than messages
for wake from S3,S4, or S5.
S1–S5
Always enabled as Wake event
S1–S5
Wake/SMI# command always enabled as a Wake event.
Note: SMBus Slave Message can wake the system from S1–
S5, as well as from S5 due to Power Button Override.
S1–S5
HOST_NOTIFY_WKEN bit SMBus Slave Command register.
Reported in the SMB_WAK_STS bit in the GPEO_STS register.
NOTES:
1.
If in the S5 state due to a powerbutton override or THRMTRIP#, the possible wake events
are due to Power Button, Hard Reset Without Cycling (See Command Type 3 in Table 5-
81), and Hard Reset System (See Command Type 4 in Table 5-81).
2.
This is a wake event from S5 only if the sleep state was entered by setting the SLP_EN and
SLP_TYP bits via software, or if there is a power failure.
3.
When the WAKE# pin is active and the PCI Express device is enabled to wake the system,
Chipset will wake the platform.
It is important to understand that the various GPIs have different levels of functionality
when used as wake events. The GPIs that reside in the core power well can only
generate wake events from sleep states where the core well is powered. Also, only
certain GPIs are “ACPI Compliant,” meaning that their Status and Enable bits reside in
ACPI I/O space. Table 5-60 summarizes the use of GPIs as wake events.
Table 5-60.GPI Wake Events
GPI
Power Well Wake From
GPI[12, 7:0]
Core
S1
GPI[15:13,11:8]
Resume
S1–S5
Notes
ACPI
Compliant
ACPI
Compliant
The latency to exit the various Sleep states varies greatly and is heavily dependent on
power supply design, so much so that the exit latencies due to Chipset are insignificant.
5.14.7.4
PCI Express* WAKE# Signal and PME Event Message
PCI Express ports can wake the platform from any sleep state (S1, S3, S4, or S5) using
the WAKE# pin. WAKE# is treated as a wake event, but does not cause any bits to go
active in the GPE_STS register.
PCI Express ports and the CPU (via DMI) have the ability to cause PME using messages.
When a PME message is received, Chipset will set the PCI_EXP_STS bit.
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