82NM10 Datasheet, PDF (545/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

EHCI Controller Registers (D29:F7)
16.2.2.6
16.2.2.7
PERIODICLISTBASE—Periodic Frame List Base Address
Register
Offset:
MEM_BASE + 34h–37h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
This 32-bit register contains the beginning address of the Periodic Frame List in the
system memory. Since the Chipset host controller operates in 64-bit mode (as
indicated by the 1 in the 64-bit Addressing Capability field in the HCCSPARAMS
register) (offset 08h, bit 0), then the most significant 32 bits of every control data
structure address comes from the CTRLDSSEGMENT register. HCD loads this register
prior to starting the schedule execution by the host controller. The memory structure
referenced by this physical memory pointer is assumed to be 4-Kbyte aligned. The
contents of this register are combined with the Frame Index Register (FRINDEX) to
enable the Host controller to step through the Periodic Frame List in sequence.
Bit
Description
31:12 Base Address (Low) — R/W. These bits correspond to memory address signals
[31:12], respectively.
11:0 Reserved. Must be written as 0s. During runtime, the value of these bits are
undefined.
ASYNCLISTADDR—Current Asynchronous List Address
Register
Offset:
MEM_BASE + 38h–3Bh
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
This 32-bit register contains the address of the next asynchronous queue head to be
executed. Since the Chipset host controller operates in 64-bit mode (as indicated by a
1 in 64-bit Addressing Capability field in the HCCPARAMS register) (offset 08h, bit 0),
then the most significant 32 bits of every control data structure address comes from
the CTRLDSSEGMENT register (offset 08h). Bits [4:0] of this register cannot be
modified by system software and will always return 0’s when read. The memory
structure referenced by this physical memory pointer is assumed to be 32-byte aligned.
Bit
Description
31:5
4:0
Link Pointer Low (LPL) — R/W. These bits correspond to memory address signals
[31:5], respectively. This field may only reference a Queue Head (QH).
Reserved. These bits are reserved and their value has no effect on operation.
Datasheet
545