82NM10 Datasheet, PDF (405/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
Table 13-127.Power Management PCI Register Address Map (PM—D31:F0)
Offset
Mnemonic
Register Name
Default
Type
A0h
A2h
A4h
A9h
AAh
ABh
ADh
B8–BBh
GEN_PMCON_1 General Power Management
Configuration 1
GEN_PMCON_2 General Power Management
Configuration 2
GEN_PMCON_3 General Power Management
Configuration 3
Cx-STATE_CNF Cx State Configuration (Netbook Only).
C4-TIMING_CNT C4 Timing Control (Netbook Only).
BM_BREAK_EN BM_BREAK_EN
MSC_FUN
Miscellaneous Functionality
GPI_ROUT
GPI Route Control
0000h
00h
00h
00h
00h
00h
00h
0000000
0h
R/W, RO,
R/WO
R/W, R/
WC
R/W, R/
WC
R/W
R/W
R/W
R/W
R/W
13.8.1.1 GEN_PMCON_1—General PM Configuration 1 Register
(PM—D31:F0)
Offset Address: A0h
Default Value: 0000h
Lockable:
No
Attribute:
Size:
Usage:
Power Well:
R/W, RO, R/WO
16-bit
ACPI, Legacy
Core
Bit
Description
15:11 Reserved
10
BIOS_PCI_EXP_EN — R/W. This bit acts as a global enable for the SCI associated
with the PCI Express* ports.
0 = The various PCI Express ports and (G)MCH/CPU cannot cause the PCI_EXP_STS
bit to go active.
1 = The various PCI Express ports and (G)MCH/CPU can cause the PCI_EXP_STS bit
to go active.
9
PWRBTN_LVL — RO. This bit indicates the current state of the PWRBTN# signal.
0 = Low.
1 = High.
8
Reserved
7
(Nettop
Only)
Reserved
7
Enter C4 When C3 Invoked (C4onC3_EN) — R/W. If this bit is set, then when
(Netbook software does a LVL3 read, the Chipset-M/Chipset-U transitions to the C4 state.
Only)
6
i64_EN. Software sets this bit to indicate that the processor is an IA_64 processor,
not an IA_32 processor. This may be used in various state machines where there
are behavioral differences.
Datasheet
405