82NM10 Datasheet, PDF (530/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

EHCI Controller Registers (D29:F7)
Bit
15
14
13
12:6
5
4
3
2
1
0
Description
SMI on BAR Enable — R/W.
0 = Disable.
1 = Enable. When this bit is 1 and SMI on BAR (D29:F7:6Ch, bit 31) is 1, then the host
controller will issue an SMI.
SMI on PCI Command Enable — R/W.
0 = Disable.
1 = Enable. When this bit is 1 and SMI on PCI Command (D29:F7:6Ch, bit 30) is 1,
then the host controller will issue an SMI.
SMI on OS Ownership Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1 AND the OS Ownership Change bit (D29:F7:6Ch, bit
29) is 1, the host controller will issue an SMI.
Reserved — RO. Hardwired to 00h
SMI on Async Advance Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Async Advance bit (D29:F7:6Ch, bit
21) is a 1, the host controller will issue an SMI immediately.
SMI on Host System Error Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Host System Error (D29:F7:6Ch, bit
20) is a 1, the host controller will issue an SMI.
SMI on Frame List Rollover Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Frame List Rollover bit (D29:F7:6Ch,
bit 19) is a 1, the host controller will issue an SMI.
SMI on Port Change Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Port Change Detect bit (D29:F7:6Ch,
bit 18) is a 1, the host controller will issue an SMI.
SMI on USB Error Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on USB Error bit (D29:F7:6Ch, bit 17) is a
1, the host controller will issue an SMI immediately.
SMI on USB Complete Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on USB Complete bit (D29:F7:6Ch, bit
16) is a 1, the host controller will issue an SMI immediately.
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Datasheet