82NM10 Datasheet, PDF (534/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

EHCI Controller Registers (D29:F7)
16.2.1.3
Note:
HCSPARAMS—Host Controller Structural Parameters
Offset:
MEM_BASE + 04h–07h
Default Value: 00104208h
Attribute:
Size:
R/W (special), RO
32 bits
This register is reset by a suspend well reset and not a D3-to-D0 reset or HCRESET.
Bit
Description
31:24 Reserved — RO. Default=0h.
23:20 Debug Port Number (DP_N) — RO (special). Hardwired to 1h indicating that the
Debug Port is on the lowest numbered port on the Chipset.
19:16 Reserved
15:12
Number of Companion Controllers (N_CC) — R/W (special). This field indicates the
number of companion controllers associated with this USB EHCI host controller.
A 0 in this field indicates there are no companion host controllers. Port-ownership hand-
off is not supported. Only high-speed devices are supported on the host controller root
ports.
A value of 1 or more in this field indicates there are companion USB UHCI host
controller(s). Port-ownership hand-offs are supported. High, Full- and Low-speed
devices are supported on the host controller root ports.
The Chipset allows the default value of 4h to be over-written by BIOS. When removing
classic controllers, they should be disabled in the following order: Function 3, Function
2, Function 1, and Function 0, which correspond to ports 7:6, 5:4, 3:2, and 1:0,
respectively.
11:8
Number of Ports per Companion Controller (N_PCC) — RO. Hardwired to 2h. This
field indicates the number of ports supported per companion host controller. It is used
to indicate the port routing configuration to system software.
7:4 Reserved. These bits are reserved and default to 0.
3:0 N_PORTS — R/W (special). This field specifies the number of physical downstream
ports implemented on this host controller. The value of this field determines how many
port registers are addressable in the Operational Register Space. Valid values are in the
range of 1h to Fh.
The Chipset reports 8h by default. However, software may write a value less than 8 for
some platform configurations. A 0 in this field is undefined.
NOTE: This register is writable when the WRT_RDONLY bit is set.
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