82NM10 Datasheet, PDF (366/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
Bit
Description
3 FDD_LPC_EN — R/W. Floppy Drive Enable
0 = Disable.
1 = Enables the decoding of the FDD range to the LPC interface. This range is selected
in the LPC_FDD/LPT Decode Range Register (D31:F0:80h, bit 12).
2 LPT_LPC_EN — R/W. Parallel Port Enable
0 = Disable.
1 = Enables the decoding of the LPTrange to the LPC interface. This range is selected in
the LPC_FDD/LPT Decode Range Register (D31:F0:80h, bit 9:8).
1 COMB_LPC_EN — R/W. Com Port B Enable
0 = Disable.
1 = Enables the decoding of the COMB range to the LPC interface. This range is
selected in the LPC_COM Decode Range Register (D31:F0:80h, bits 6:4).
0 COMA_LPC_EN — R/W. Com Port A Enable
0 = Disable.
1 = Enables the decoding of the COMA range to the LPC interface. This range is
selected in the LPC_COM Decode Range Register (D31:F0:80h, bits 3:2).
13.1.22 GEN1_DEC—LPC I/F Generic Decode Range 1 Register
(LPC I/F—D31:F0)
Offset Address: 84h – 87h
Default Value: 00000000h
Attribute:
Size:
Power Well:
R/W
32 bit
Core
Bit
Description
31:24 Reserved
23:18
Generic I/O Decode Range Address[7:2] Mask: A ‘1’ in any bit position indicates
that any value in the corresponding address bit in a received cycle will be treated as a
match. The corresponding bit in the Address field, below, is ignored. The mask is only
provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to
256 bytes in size.
17:16 Reserved
15:2 Generic I/O Decode Range 1 Base Address (GEN1_BASE) — R/W. This address
is aligned on a 128-byte boundary, and must have address lines 31:16 as 0.
NOTE: The Chipset does not provide decode down to the word or byte level.
1 Reserved
0 Generic Decode Range 1 Enable (GEN1_EN) — R/W.
0 = Disable.
1 = Enable the GEN1 I/O range to be forwarded to the LPC I/F
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