82NM10 Datasheet, PDF (536/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

EHCI Controller Registers (D29:F7)
Table 16-142.Enhanced Host Controller Operational Register Address Map
MEM_BAS
E + Offset
Mnemonic
Register Name
20h–23h
24h–27h
28h–2Bh
2Ch–2Fh
30h–33h
34h–37h
38h–3Bh
3Ch–5Fh
60h–63h
64h–67h
USB2.0_CMD USB 2.0 Command
USB2.0_STS USB 2.0 Status
USB2.0_INTR USB 2.0 Interrupt Enable
FRINDEX USB 2.0 Frame Index
CTRLDSSEGM Control Data Structure
ENT
Segment
PERODICLIST Period Frame List Base
BASE
Address
ASYNCLISTAD Current Asynchronous List
DR
Address
—
Reserved
CONFIGFLAG Configure Flag
PORT0SC Port 0 Status and Control
68h–6Bh
PORT1SC Port 1 Status and Control
6Ch–6Fh
PORT2SC Port 2 Status and Control
70h–73h
PORT3SC Port 3 Status and Control
74h–77h
PORT4SC Port 4 Status and Control
78h–7Bh
PORT5SC Port 5 Status and Control
7Ch–7Fh
PORT6SC Port 6 Status and Control
80h–83h
PORT7SC Port 7 Status and Control
84h–9Fh
A0h–B3h
—
Reserved
—
Debug Port Registers
B4h–3FFh
—
Reserved
Default
Special
Notes
00080000h
00001000h
00000000h
00000000h
00000000h
Type
R/W, RO
R/WC, RO
R/W
R/W,
R/W, RO
00000000h
R/W
00000000h
R/W
0h
RO
00000000h Suspend
R/W
00003000h Suspend
R/W,
R/WC, RO
00003000h Suspend
R/W,
R/WC, RO
00003000h Suspend
R/W,
R/WC, RO
00003000h Suspend
R/W,
R/WC, RO
00003000h Suspend
R/W,
R/WC, RO
00003000h Suspend
R/W,
R/WC, RO
00003000h Suspend
R/W,
R/WC, RO
00003000h Suspend
R/W,
R/WC, RO
Undefined
RO
Undefined
See
register
description
Undefined
RO
Note:
Software must read and write these registers using only DWord accesses.These
registers are divided into two sets. The first set at offsets MEM_BASE + 00:3Bh are
implemented in the core power well. Unless otherwise noted, the core well registers are
reset by the assertion of any of the following:
• Core well hardware reset
• HCRESET
536
Datasheet