82NM10 Datasheet, PDF (475/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
15.1.9
PMLT—Primary Master Latency Timer Register
(SATA–D31:F2)
Address Offset: 0Dh
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0 Master Latency Timer Count (MLTC) — RO.
00h = Hardwired. The SATA controller is implemented internally, and is not arbitrated
as a PCI device, so it does not need a Master Latency Timer.
15.1.10 PCMD_BAR—Primary Command Block Base Address
Register (SATA–D31:F2)
Address Offset: 10h–13h
Default Value: 00000001h
Attribute:
Size:
R/W, RO
32 bits
.
Bit
Description
31:16 Reserved
15:3 Base Address — R/W. This field provides the base address of the I/O space (8
consecutive I/O locations).
2:1 Reserved
0 Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O
space.
NOTE: This 8-byte I/O space is used in native mode for the Primary Controller’s Command Block.
15.1.11 PCNL_BAR—Primary Control Block Base Address Register
(SATA–D31:F2)
Address Offset: 14h–17h
Default Value: 00000001h
Attribute:
Size:
R/W, RO
32 bits
.
Bit
Description
31:16 Reserved
15:2 Base Address — R/W. This field provides the base address of the I/O space (4
consecutive I/O locations).
1 Reserved
0 Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O
space.
NOTE: This 4-byte I/O space is used in native mode for the Primary Controller’s Command Block.
Datasheet
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