82NM10 Datasheet, PDF (61/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Signal Description
2.22 Pin Straps
2.22.1
Functional Straps
The following signals are used for static configuration. They are sampled at the rising
edge of PWROK to select configurations (except as noted), and then revert later to their
normal usage. To invoke the associated mode, the signal should be driven at least four
PCI clocks prior to the time it is sampled.
Table 2-24.Functional Strap Definitions (Sheet 1 of 2)
Signal
Usage
When
Sampled
Comment
HDA_SDOUT
PCI
Express*
Port Config
bit 1
Rising Edge of
PWROK
When TP3 not pulled low at rising edge of
PWROK, sets bit 1 of RPC.PC (Chipset
Configuration Registers:Offset 224h). See
Section 10.1.30 for details.
This signal has a weak internal pull-down.
HDA_SYNC
PCI Express
Port Config
bit 0
Rising Edge of
PWROK
This signal has a weak internal pull-down.
Sets bit 0 of RPC.PC (Chipset Configuration
Registers:Offset 224h). See Section 10.1.30 for
details.
EE_CS
Reserved
This signal has a weak internal pull-down.
NOTE: This signal should not be pulled high.
EE_DOUT
Reserved
This signal has a weak internal pull-up.
NOTE: This signal should not be pulled low.
GNT2#
Reserved
This signal has a weak internal pull-up.
NOTE: This signal should not be pulled low.
STRAP0#
Top-Block
Swap
Override
Rising Edge of
PWROK
The signal has a weak internal pull-up. If the
signal is sampled low, this indicates that the
system is strapped to the “top-block swap” mode
(the chipset inverts A16 for all cycles targeting
FWH BIOS space). The status of this strap is
readable via the Top Swap bit (Chipset
Configuration Registers:Offset 3414h:bit 0).
Note that software will not be able to clear the
Top-Swap bit until the system is rebooted
without STRAP0# being pulled down.
STRAP2# /
GPIO17,
STRAP1# /
GPIO48
Boot BIOS
Destination
Selection
Rising Edge of
PWROK
This field determines the destination of accesses
to the BIOS memory range. Signals have weak
internal pull-ups. Also controllable via Boot BIOS
Destination bit (Chipset Configuration
Registers:Offset 3410h:bit 11:10)
(STRAP2# is MSB)
01 = SPI
10 = PCI
11 = LPC
DPRSLPVR
Reserved
This signal has a weak internal pull-down.
NOTE: This signal should not be pulled high.
Datasheet
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