82NM10 Datasheet, PDF (165/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
— An alert message indicating that the processor is missing or locked up is
generated with a new sequence number.
Table 5-68 shows the data included in the Alert on LAN messages.
Table 5-68.Heartbeat Message Data
Field
Comment
Cover Tamper Status
1 = This bit is set if the intruder detect bit is set (INTRD_DET).
Temp Event Status
1 = This bit is set if Chipset THERM# input signal is asserted.
Processor Missing Event 1 = This bit is set if the processor failed to fetch its first instruction.
Status
TCO Timer Event Status 1 = This bit is set when the TCO timer expires.
Software Event Status 1 = This bit is set when software writes a 1 to the SEND_NOW bit.
Unprogrammed
Firmware Hub Event
Status
1 = First BIOS fetch returned a value of FFh, indicating that the
Firmware Hub has not yet been programmed (still erased).
GPIO Status
1 = This bit is set when GPIO11 signal is high.
0 = This bit is cleared when GPIO11 signal is low.
An event message is triggered on an transition of GPIO11.
SEQ[3:0]
This is a sequence number. It initially is 0, and increments each time
Chipset sends a new message. Upon reaching 1111, the sequence
number rolls over to 0000. MSB (SEQ3) sent first.
System Power State
00 = G0, 01 = G1, 10 = G2, 11 = Pre-Boot. MSB sent first
MESSAGE1
Will be the same as the MESSAGE1 Register. MSB sent first.
MESSAGE2
Will be the same as the MESSAGE2 Register. MSB sent first.
WDSTATUS
Will be the same as the WDSTATUS Register. MSB sent first.
5.16
SATA Host Controller (D31:F2)
The SATA function in Chipset has dual modes of operation to support different operating
system conditions. In the case of Native IDE enabled operating systems, Chipset
unitize single controllers to enable two ports of the bus.
The MAP register, Section 15.1.33, provides the ability to share PCI functions. When
sharing is enabled, all decode of I/O is done through the SATA registers. Device 31,
Function 1 (IDE controller) is hidden by software writing to the Function Disable
Register (D31, F0, offset F2h, bit 1), and its configuration registers are not used.
Chipset SATA controller features two sets of interface signals (ports) that can be
independently enabled or disabled (they cannot be tri-stated or driven low). Each
interface is supported by an independent DMA controller.
Chipset SATA controller interacts with an attached mass storage device through a
register interface that is equivalent to that presented by a traditional IDE host adapter.
The host software follows existing standards and conventions when accessing the
register interface and follows standard command protocol conventions.
Datasheet
165