82NM10 Datasheet, PDF (170/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
2. When the power state is D3, no interrupts may be generated, even if they are
enabled. If an interrupt status bit is pending when the controller transitions to D0,
an interrupt may be generated.
When the controller is put into D3, it is assumed that software has properly shut down
the device and disabled the ports. Therefore, there is no need to sustain any values on
the port wires. The interface will be treated as if no device is present on the cable, and
power will be minimized.
When returning from a D3 state, an internal reset will not be performed.
5.16.3.2.4 Non-AHCI Mode PME# Generation
When in non-AHCI mode (legacy mode) of operation, the SATA controller does not
generate PME#. This includes attach events (since the port must be disabled), or
interlock switch events (via the SATAGP pins).
5.16.3.3
SMI Trapping (APM)
Device 31:Function2:Offset C0h (see Section 15.1.40) contain control for generating
SMI# on accesses to the IDE I/O spaces. These bits map to the legacy ranges (1F0–
1F7h, 3F6h, 170–177h, and 376h). If the SATA controller is in legacy mode and is using
these addresses, accesses to one of these ranges with the appropriate bit set causes
the cycle to not be forwarded to the SATA controller, and for an SMI# to be generated.
If an access to the Bus-Master IDE registers occurs while trapping is enabled for the
device being accessed, then the register is updated, an SMI# is generated, and the
device activity status bits (Section 15.1.41) are updated indicating that a trap
occurred.
5.16.4
SATA LED
The SATALED# output is driven whenever the BSY bit is set in any SATA port. The
SATALED# is an active-low open-collector output. When SATALED# is low, the LED
should be active. When SATALED# is high, the LED should be inactive.
5.16.5
AHCI Operation
Chipset provides hardware support for Advanced Host Controller Interface (AHCI), a
programming interface for SATA host controllers developed thru a joint industry effort.
AHCI defines transactions between the SATA controller and software and enables
advanced performance and usability with SATA. Platforms supporting AHCI may take
advantage of performance features such as no master/slave designation for SATA
devices—each device is treated as a master—and hardware assisted native command
queuing. AHCI also provides usability enhancements such as Hot-Plug. AHCI requires
appropriate software support (e.g., an AHCI driver) and for some features, hardware
support in the SATA device or additional platform hardware.
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Datasheet