82NM10 Datasheet, PDF (502/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
15.3.1.3
15.3.1.4
Bit
Description
30:2
1
0
Reserved. Returns 0.
Interrupt Enable (IE) — R/W. This global bit enables interrupts from the Chipset.
0 = All interrupt sources from all ports are disabled.
1 = Interrupts are allowed from the AHCI controller.
HBA Reset (HR) — R/W. Resets Chipset AHCI controller.
0 = No effect
1 = Causes an internal reset of the Chipset AHCI controller. All state machines that
relate to data transfers and queuing return to an idle condition, and all ports are
re-initialized via COMRESET.
NOTE: For further details, consult section 12.3.3 of the Serial ATA Advanced Host
Controller Interface specification.
IS—Interrupt Status Register (D31:F2)
Address Offset: ABAR + 08h–0Bh
Default Value: 00000000h
Attribute:
Size:
R/WC, RO
32 bits
This register indicates which of the ports within the controller have an interrupt pending
and require service.
Bit
31:2
1
0
Description
Reserved. Returns 0.
Interrupt Pending Status Port[1] (IPS[1]) — R/WC.
0 = No interrupt pending.
1 = Port 1has an interrupt pending. Software can use this information to determine
which ports require service after an interrupt.
Interrupt Pending Status Port[0] (IPS[0]) — R/WC.
0 = No interrupt pending.
1 = Port 0 has an interrupt pending. Software can use this information to determine
which ports require service after an interrupt.
PI—Ports Implemented Register (D31:F2)
Address Offset: ABAR + 0Ch–0Fh
Default Value: 00000000h
Attribute:
Size:
R/WO, RO
32 bits
This register indicates which ports are exposed to the Chipset. It is loaded by platform
BIOS. It indicates which ports that the device supports are available for software to
use. For ports that are not available, software must not read or write to registers within
that port.
Bit
31:2
1
Description
Reserved. Returns 0.
Ports Implemented Port 1 (PI1) — R/WO.
0 = The port is not implemented.
1 = The port is implemented.
502
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