82NM10 Datasheet, PDF (204/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
5.20.5
Note:
5.20.6
5.20.7
SMBALERT#
SMBALERT# is multiplexed with GPIO11. When enable and the signal is asserted,
Chipset can generate an interrupt, an SMI#, or a wake event from S1–S5.
Any event on SMBALERT# (regardless whether it is programmed as a GPI or not),
causes the event message to be sent in heartbeat mode.
SMBus CRC Generation and Checking
If the AAC bit is set in the Auxiliary Control register, Chipset automatically calculates
and drives CRC at the end of the transmitted packet for write cycles, and will check the
CRC for read cycles. It will not transmit the contents of the PEC register for CRC. The
PEC bit must not be set in the Host Control register if this bit is set, or unspecified
behavior will result.
If the read cycle results in a CRC error, the DEV_ERR bit and the CRCE bit in the
Auxiliary Status register at offset 0Ch will be set.
SMBus Slave Interface
Chipset’s SMBus Slave interface is accessed via the SMBus. The SMBus slave logic will
not generate or handle receiving the PEC byte and will only act as a Legacy Alerting
Protocol device. The slave interface allows Chipset to decode cycles, and allows an
external microcontroller to perform specific actions. Key features and capabilities
include:
• Supports decode of three types of messages: Byte Write, Byte Read, and Host
Notify.
• Receive Slave Address register: This is the address that Chipset decodes. A default
value is provided so that the slave interface can be used without the processor
having to program this register.
• Receive Slave Data register in the SMBus I/O space that includes the data written
by the external microcontroller.
• Registers that the external microcontroller can read to get the state of Chipset.
• Status bits to indicate that the SMBus slave logic caused an interrupt or SMI# due
to the reception of a message that matched the slave address.
— Bit 0 of the Slave Status Register for the Host Notify command
— Bit 16 of the SMI Status Register (Section 13.8.3.13) for all others
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Datasheet