82NM10 Datasheet, PDF (506/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
15.3.2.5
PxIS—Port [1:0] Interrupt Status Register (D31:F2)
Address Offset: Port 0: ABAR + 110h
Port 1: ABAR + 190h
Default Value: 00000000h
Attribute:
Size:
R/WC, RO
32 bits
Bit
Description
31
30
29
28
27
26
25
24
23
22
21:8
7
6
5
Cold Port Detect Status (CPDS) — RO. Cold presence not supported.
Task File Error Status (TFES) — R/WC. This bit is set whenever the status register is
updated by the device and the error bit (PxTFD.bit 0) is set.
Host Bus Fatal Error Status (HBFS) — R/WC. Indicates that the Chipset
encountered an error that it cannot recover from due to a bad software pointer. In PCI,
such an indication would be a target or master abort.
Host Bus Data Error Status (HBDS) — R/WC. Indicates that the Chipset
encountered a data error (uncorrectable ECC / parity) when reading from or writing to
system memory.
Interface Fatal Error Status (IFS) — R/WC. Indicates that the Chipset encountered
an error on the SATA interface which caused the transfer to stop.
Interface Non-fatal Error Status (INFS) — R/WC. Indicates that the Chipset
encountered an error on the SATA interface but was able to continue operation.
Reserved
Overflow Status (OFS) — R/WC. Indicates that the Chipset received more bytes from
a device than was specified in the PRD table for the command.
Incorrect Port Multiplier Status (IPMS) — R/WC. Indicates that the Chipset
received a FIS from a device whose Port Multiplier field did not match what was
expected.
NOTE: Port Multiplier not supported by Chipset.
PhyRdy Change Status (PRCS) — RO. When set to one indicates the internal PhyRdy
signal changed state. This bit reflects the state of PxSERR.DIAG.N. Unlike most of the
other bits in the register, this bit is RO and is only cleared when PxSERR.DIAG.N is
cleared.
Note that the internal PhyRdy signal also transitions when the port interface enters
partial or slumber power management states. Partial and slumber must be disabled
when Surprise Removal Notification is desired, otherwise the power management state
transitions will appear as false insertion and removal events.
Reserved
Device Interlock Status (DIS) — R/WC. When set, indicates that a platform interlock
switch has been opened or closed, which may lead to a change in the connection state
of the device.This bit is only valid in systems that support an interlock switch (CAP.SIS
[ABAR+00:bit 28] set).
For systems that do not support an interlock switch, this bit will always be 0.
Port Connect Change Status (PCS) — RO. This bit reflects the state of
PxSERR.DIAG.X. (ABAR+130h/1D0h/230h/2D0h, bit 26) Unlike other bits in this
register, this bit is only cleared when PxSERR.DIAG.X is cleared.
0 = No change in Current Connect Status.
1 = Change in Current Connect Status.
Descriptor Processed (DPS) — R/WC. A PRD with the I bit set has transferred all its
data.
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