82NM10 Datasheet, PDF (57/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Signal Description
2.17 Miscellaneous Signals
Table 2-19.Miscellaneous Signals
Name
Type
Description
INTVRMEN
SPKR
Internal Voltage Regulator Enable: This signal must always
I connected to VccRTC to make sure the internal 1.05 V Suspend
regulator is been enabled.
Speaker: The SPKR signal is the output of counter 2 and is internally
“ANDed” with Port 61h bit 1 to provide Speaker Data Enable. This
signal drives an external speaker driver device, which in turn drives the
O system speaker. Upon PLTRST#, its output state is 0.
NOTE: SPKR is sampled at the rising edge of PWROK as a functional
strap. See Section 2.22.1 for more details. There is a weak
integrated pull-down resistor on SPKR pin.
RTC Reset: When asserted, this signal resets register bits in the RTC
well.
RTCRST#
STRAP0
STRAP[1]#/
GPIO48
STRAP[2]#/
GPIO17
NOTES:
I 1.
Unless CMOS is being cleared (only to be done in the G3 power
state), the RTCRST# input must be high when all other RTC
power planes are on.
2.
In the case where the RTC battery is dead or missing on the
platform, the RTCRST# pin must rise before the RSMRST# pin.
O
Strapping 0: This pin have strapping function use as “Top-Block Swap
Override”.
Strapping 1: This pin have strapping function use as “Boot BIOS
O Destination Selection”.
The STRAP[1]# pin can instead be used as a GPIO.
Strapping 2: This pin have strapping function use as “Boot BIOS
O Destination Selection”.
The STRAP[2]# pin can instead be used as a GPIO.
2.18 Intel HD Audio Link
Table 2-20.Intel HD Audio Link Signals (Sheet 1 of 2)
Name^1,2
Type
Description
HDA_RST#
HDA_SYNC
HDA_BIT_CLK
O
Intel HD Audio Reset: This signal is the master hardware reset to
external codec(s).
Intel High Definition Audio Sync: This signal is a 48 kHz fixed
O rate sample sync to the codec(s). It is also used to encode the
stream number.
Intel High Definition Audio Bit Clock Output: This signal is a
24.000 MHz serial data clock generated by the Intel High Definition
O Audio controller. This signal has an integrated pull-down resistor so
that HDA_BIT_CLK doesn’t float when an Intel High Definition Audio
codec (or no codec) is connected.
Datasheet
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