82NM10 Datasheet, PDF (270/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Chipset Configuration Registers
10.1.9
V1CAP—Virtual Channel 1 Resource Capability Register
Offset Address: 001C–001Fh
Default Value: 30008010h
Attribute:
Size:
R/WO, RO
32-bit
Bit
Description
31:24
23
22:16
15
14
13:8
7:0
Port Arbitration Table Offset (AT) — RO. This field indicates the location of the
port arbitration table in the root complex. A value of 3h indicates the table is at offset
30h.
Reserved
Maximum Time Slots (MTS) — R/WO. This value is updated by platform BIOS
based upon the determination of the number of time slots available in the platform.
Reject Snoop Transactions (RTS) — RO. All snoopable transactions on VC1 are
rejected. This VC is for isochronous transfers only.
Advanced Packet Switching (APS) — RO. This VC is capable of all transactions,
not just advanced packet switching transactions.
Reserved
Port Arbitration Capability (PAC) — RO. This field indicates the port arbitration
capability is time-based WRR of 128 phases.
10.1.10 V1CTL—Virtual Channel 1 Resource Control Register
Offset Address: 0020–0023h
Default Value: 00000000h
Attribute:
Size:
R/W, RO
32-bit
Bit
Description
31
30:27
26:24
23:20
19:17
16
15:8
7:1
0
Virtual Channel Enable (EN) — R/W.
0 = Disables the VC.
1 = Enables the VC.
Reserved
Virtual Channel Identifier (ID) — R/W. This field indicates the ID to use for this virtual
channel.
Reserved
Port Arbitration Select (PAS) — R/W. This field indicates which port table is being
programmed. The only permissible value of this field is 4h for the time-based WRR
entries.
Load Port Arbitration Table (LAT) — RO/W. When set, the port arbitration table
loaded is based upon the PAS field in this register. This bit always returns 0 when
read.
Reserved
Transaction Class / Virtual Channel Map (TVM) — R/W. This field indicates
which transaction classes are mapped to this virtual channel. When a bit is set, this
transaction class is mapped to the virtual channel.
Reserved
270
Datasheet