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82NM10 Datasheet, PDF (472/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset | |||
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SATA Controller Registers (D31:F2)
Bit
Description
2 Bus Master Enable (BME) â R/W. This bit controls the chipsetâs ability to act as a PCI
master for IDE Bus Master transfers. This bit does not impact the generation of
completions for split transaction commands.
1 Memory Space Enable (MSE) â R/W / RO. This bit controls access to the SATA
controllerâs target memory space (for AHCI).
0 I/O Space Enable (IOSE) â R/W. This bit controls access to the I/O space registers.
0 = Disables access to the Legacy or Native IDE ports (both Primary and Secondary) as
well as the Bus Master I/O registers.
1 = Enable. Note that the Base Address register for the Bus Master registers should be
programmed before this bit is set.
15.1.4
Note:
PCISTS â PCI Status Register (SATAâD31:F2)
Address Offset: 06hâ07h
Default Value: 02B0h
Attribute:
Size:
R/WC, RO
16 bits
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit
15
14
13
12
11
10:9
8
7
6
5
Description
Detected Parity Error (DPE) â R/WC.
0 = No parity error detected by SATA controller.
1 = SATA controller detects a parity error on its interface.
Signaled System Error (SSE) â RO. Reserved as 0.
Received Master Abort (RMA) â R/WC.
0 = Master abort Not generated.
1 = SATA controller, as a master, generated a master abort.
Reserved as 0 â RO.
Signaled Target Abort (STA) â RO. Reserved as 0.
DEVSEL# Timing Status (DEV_STS) â RO.
01 = Hardwired; Controls the device select time for the SATA controllerâs PCI interface.
Data Parity Error Detected (DPED) â RO. For Chipset, this bit can only be set on
read completions received from SiBUS where there is a parity error.
0 = Data parity error Not detected.
1 = SATA controller, as a master, either detects a parity error or sees the parity error
line asserted, and the parity error response bit (bit 6 of the command register) is
set.
Fast Back to Back Capable (FB2BC) â RO. Reserved as 1.
User Definable Features (UDF) â RO. Reserved as 0.
66MHz Capable (66MHZ_CAP) â RO. Reserved as 1.
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Datasheet
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