82NM10 Datasheet, PDF (451/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

UHCI Controllers Registers
Bit
Description
3 Special Cycle Enable (SCE) — RO. Hardwired to 0.
2 Bus Master Enable (BME) — R/W.
0 = Disable
1 = Enable. Chipset can act as a master on the PCI bus for USB transfers.
1 Memory Space Enable (MSE) — RO. Hardwired to 0.
0 I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.
0 = Disable
1 = Enable accesses to the USB I/O registers. The Base Address register for USB should
be programmed before this bit is set.
14.1.4
Note:
PCISTS—PCI Status Register
(USB—D29:F0/F1/F2/F3)
Address Offset:
06h–07hAttribute:R/WC, RO
Default Value:
0280hSize:16 bits
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit
15
14
13
12
11
10:9
8
7
6
5
Description
Detected Parity Error (DPE) — R/WC.
0 = No parity error detected.
1 = Set when a data parity error data parity error is detected on writes to the UHCI
register space or on read completions returned to the host controller.
Reserved as 0b. Read Only.
Received Master Abort (RMA) — R/WC.
0 = No master abort generated by USB.
1 = USB, as a master, generated a master abort.
Reserved. Always read as 0.
Signaled Target Abort (STA) — R/WC.
0 = Chipset did Not terminate transaction for USB function with a target abort.
1 = USB function is targeted with a transaction that the Chipset terminates with a
target abort.
DEVSEL# Timing Status (DEV_STS) — RO. This 2-bit field defines the timing for
DEVSEL# assertion. These read only bits indicate the Chipset's DEVSEL# timing when
performing a positive decode. Chipset generates DEVSEL# with medium timing for
USB.
Data Parity Error Detected (DPED) — RO. Hardwired to 0.
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1.
User Definable Features (UDF) — RO. Hardwired to 0.
66 MHz Capable — RO. Hardwired to 0.
Datasheet
451