82NM10 Datasheet, PDF (52/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Signal Description
2.11 Power Management Interface
Table 2-13.Power Management Interface Signals (Sheet 1 of 3)
Name
Type
Description
PLTRST#
THRM#
THRMTRIP#
SLP_S3#
SLP_S4#
SLP_S5#
PWROK
PWRBTN#
RI#
Platform Reset: The chipset asserts PLTRST# to reset devices on
the platform (e.g., SIO, FWH, LAN, (G)MCH, IDE, TPM, etc.). The
chipset asserts PLTRST# during power-up and when S/W initiates a
hard reset sequence through the Reset Control register (I/O Register
O CF9h). The chipset drives PLTRST# inactive a minimum of 1 ms after
both PWROK and VRMPWRGD are driven high. The chipset drives
PLTRST# active a minimum of 1 ms when initiated through the Reset
Control register (I/O Register CF9h).
NOTE: PLTRST# is in the VccSus3_3 well.
I
Thermal Alarm: THRM# is an active low signal generated by
external hardware to generate an SMI# or SCI.
Thermal Trip: When low, this signal indicates that a thermal trip
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from the processor occurred, and the chipset will immediately
transition to a S5 state. The chipset will not wait for the processor
stop grant cycle since the processor has overheated.
S3 Sleep Control: SLP_S3# is for power plane control. This signal
O shuts off power to all non-critical systems when in S3 (Suspend To
RAM), S4 (Suspend to Disk), or S5 (Soft Off) states.
S4 Sleep Control: SLP_S4# is for power plane control. This signal
shuts power to all non-critical systems when in the S4 (Suspend to
O
Disk) or S5 (Soft Off) state.
NOTE: This pin must be used to control the DRAM power to use
chipset’s DRAM power-cycling feature. Refer to
Chapter 5.14.11.2 for details.
S5 Sleep Control: SLP_S5# is for power plane control. This signal is
O used to shut power off to all non-critical systems when in the S5
(Soft Off) states.
Power OK: When asserted, PWROK is an indication to the chipset
that core power has been stable for 99 ms and that PCICLK has been
stable for 1 ms. An exception to this rule is if the system is in S3_HOT,
in which PWROK may or may not stay asserted even though PCICLK
I may be inactive. PWROK can be driven asynchronously. When
PWROK is negated, the chipset asserts PLTRST#.
NOTE: PWROK must deassert for a minimum of three RTC clock
periods for the chipset to fully reset the power and properly
generate the PLTRST# output.
Power Button: The Power Button will cause SMI# or SCI to indicate
a system request to go to a sleep state. If the system is already in a
sleep state, this signal will cause a wake event. If PWRBTN# is
I pressed for more than 4 seconds, this will cause an unconditional
transition (power button override) to the S5 state. Override will occur
even if the system is in the S1-S4 states. This signal has an internal
pull-up resistor and has an internal 16 ms de-bounce on the input.
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Ring Indicate: This signal is an input from a modem. It can be
enabled as a wake event, and this is preserved across power failures.
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