82NM10 Datasheet, PDF (568/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SMBus Controller Registers (D31:F3)
Bit
Description
7:3 Reserved
2 SMLINK_CLK_CTL — R/W.
0 = Chipset will drive the SMLINK0 pin low, independent of what the other SMLINK
logic would otherwise indicate for the SMLINK0 pin.
1 = The SMLINK0 pin is not overdriven low. The other SMLINK logic controls the state
of the pin. (Default)
1 SMLINK1_CUR_STS — RO. This read-only bit has a default value that is dependent on
an external signal level. This pin returns the value on the SMLINK1 pin. This allows
software to read the current state of the pin.
0 = Low
1 = High
0 SMLINK0_CUR_STS — RO. This read-only bit has a default value that is dependent on
an external signal level. This pin returns the value on the SMLINK0 pin. This allows
software to read the current state of the pin.
0 = Low
1 = High
17.2.14 SMBUS_PIN_CTL—SMBUS Pin Control Register
(SMBUS—D31:F3)
Register Offset: SMBASE + 0Fh
Default Value: See below
Attribute:
Size:
R/W, RO
8 bits
Note:
This register is in the resume well and is reset by RSMRST#.
Bit
Description
7:3 Reserved
2 SMBCLK_CTL — R/W.
1 = The SMBCLK pin is not overdriven low. The other SMBus logic controls the state of
the pin.
0 = Chipset drives the SMBCLK pin low, independent of what the other SMB logic would
otherwise indicate for the SMBCLK pin. (Default)
1 SMBDATA_CUR_STS — RO. This read-only bit has a default value that is dependent
on an external signal level. This pin returns the value on the SMBDATA pin. This allows
software to read the current state of the pin.
0 = Low
1 = High
0 SMBCLK_CUR_STS — RO. This read-only bit has a default value that is dependent on
an external signal level. This pin returns the value on the SMBCLK pin. This allows
software to read the current state of the pin.
0 = Low
1 = High
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Datasheet