82NM10 Datasheet, PDF (423/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
13.8.3.8
LV4—Level 4 Register (Netbook Only)
I/O Address:
Default Value:
Lockable:
PMBASE + 16h (ACPI P_BLK + 6)
Attribute:
00h
Size:
No
Usage:
Power Well:
RO
8-bit
ACPI or Legacy
Core
Bit
Description
7:0 Reads to this register return all 0s, writes to this register have no effect. Reads to this
register generate a “enter a C4 power state” to the clock control logic. The C4 state
persists until a break event occurs.
NOTE: This register should not be used by iA64 processors or systems with more than 1 logical
processor, unless appropriate semaphoring software has been put in place to ensure that
all threads/processors are ready for the C4 state when the “read to this register”
instruction occurs.
13.8.3.9
PM2_CNT—Power Management 2 Control Register (Netbook Only)
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 20h
(ACPI PM2_BLK)
00h
No
Core
Attribute:
Size:
Usage:
R/W
8-bit
ACPI
Bit
Description
7:1 ^Reserved
0 ^{Arbiter Disable (ARB_DIS) — R/W. This bit is a scratchpad bit for legacy software}
compatibility. Software typically sets this bit to 1 prior to entering a C3 or C4 state.
When a transition to a C3 or C4 state occurs, Chipset on Netbook platform will
automatically prevent any internal or external non-Isoch bus masters from initiating
any cycles up to the (G)MCH/CPU. This blocking starts immediately upon the Chipset
sending the Go–C3 message to the (G)MCH/CPU. The blocking stops when the Ack-C2
message is received. Note that this is not really blocking, in that messages (such as
from PCI Express*) are just queued and held pending.
13.8.3.10 GPE0_STS—General Purpose Event 0 Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 28h
(ACPI GPE0_BLK)
00000000h
No
Resume
Attribute:
Size:
Usage:
R/WC
32-bit
ACPI
This register is symmetrical to the General Purpose Event 0 Enable Register. Unless
indicated otherwise below, if the corresponding _EN bit is set, then when the _STS bit
get set, the Chipset will generate a Wake Event. Once back in an S0 state (or if already
in an S0 state when the event occurs), the Chipset will also generate an SCI if the
SCI_EN bit is set, or an SMI# if the SCI_EN bit (PMBASE + 04h, bit 0) is not set. Bits
31:16 are reset by a CF9h write; bits 15:0 are not. All are reset by RSMRST#.
Datasheet
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