82NM10 Datasheet, PDF (133/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
5.13.2 Dual-Processor Issues (Nettop Only)
5.13.2.1
Signal Differences
In dual-processor designs, some of the processor signals are unused or used differently
than for uniprocessor designs.
Table 5-52.DP Signal Differences
Signal
Difference
A20M# / A20GATE
STPCLK#
FERR# / IGNNE#
Generally not used, but still supported by Chipset.
Used for S1 State as well as preparation for entry to S3–S5
Also allows for THERM# based throttling (not via ACPI control methods).
Should be connected to both processors.
Generally not used, but still supported by Chipset.
5.13.2.2 Power Management
For Dual-processor configurations in which more than one Stop Grant cycle may be
generated, the CPU is expected to count Stop Grant cycles and only pass the last one
through to Chipset. This prevents Chipset from getting out of sync with the processor
on multiple STPCLK# assertions.
Because the S1 state will have the STPCLK# signal active, the STPCLK# signal can be
connected to both processors. However, for ACPI implementations, the BIOS must
indicate that Chipset only supports the C1 state for dual-processor designs.
In going to the S1 state for Nettop, multiple Stop-Grant cycles will be generated by the
processors. Chipset also has the option to assert the processor’s SLP# signal
(CPUSLP#). It is assumed that prior to setting the SLP_EN bit (which causes the
transition to the S1 state), the processors will not be executing code that is likely to
delay the Stop-Grant cycles.
In going to the S3, S4, or S5 states, the system will appear to pass through the S1
state; thus, STPCLK# and SLP# are also used. During the S3, S4, and S5 states, both
processors will lose power. Upon exit from those states, the processors will have their
power restored.
5.14 Power Management (D31:F0)
5.14.1
Features
• Support for Advanced Configuration and Power Interface, Version 2.0 (ACPI)
providing power and thermal management
— ACPI 24-Bit Timer
— Software initiated throttling of processor performance for Thermal and Power
Reduction
Datasheet
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