82NM10 Datasheet, PDF (180/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
Note:
The scheme described below assumes that the keyboard controller (8042 or
equivalent) is on the LPC bus.
This legacy operation is performed through SMM space. Figure 5-14 shows the Enable
and Status path. The latched SMI source (60R, 60W, 64R, 64W) is available in the
Status Register. Because the enable is after the latch, it is possible to check for other
events that didn't necessarily cause an SMI. It is the software's responsibility to
logically AND the value with the appropriate enable bits.
Note also that the SMI is generated before the PCI cycle completes (e.g., before TRDY#
goes active) to ensure that the processor doesn't complete the cycle before the SMI is
observed. This method is used on MPIIX and has been validated.
The logic also needs to block the accesses to the 8042. If there is an external 8042,
then this is simply accomplished by not activating the 8042 CS. This is simply done by
logically ANDing the four enables (60R, 60W, 64R, 64W) with the 4 types of accesses to
determine if 8042CS should go active. An additional term is required for the “pass-
through” case.
The state table for the diagram is shown in Table 5-73.
Figure 5-14. USB Legacy Keyboard Flow Diagram
KBC Accesses
PCI Config
Read, Write
Comb.
Decoder
60 READ
S
D
Clear SMI_60_R
R
EN_SMI_ON_60R
AND
Same for 60W, 64R, 64W
To Individual
"Caused By"
"Bits"
SMI
OR
EN_PIRQD#
AND
To PIRQD#
USB_IRQ
Clear USB_IRQ
S
D
R
EN_SMI_ON_IRQ
AND
To "Caused By" Bit
180
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