PXD20RM Datasheet, PDF (998/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

27.10.13 LIN control register 2 (LINCR2)
Offset: 0x30
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0
WUR DDR DTR ABR HTR
QQQQQ
0
0
0
0
0
0
0
0
W
w1c w1c w1c w1c w1c
Reset 0
1 0/1² 0
0
0
0
0
0
0
0
0
0
0
0
0
1 _{These fields are writable only in Initialization mode (LINCR1[INIT] = 1.}
2 _{Resets to 1 in Slave mode and to 0 in Master mode}
Figure 27-30. LIN control register 2 (LINCR2)
Table 27-27. LINCR2 field descriptions
Field
IOBE
IOPE
WURQ
DDRQ
DTRQ
Description
Idle on Bit Error
0: Bit error does not reset LIN state machine
1: Bit error reset LIN state machine
This bit can be set/cleared in Initialization mode only (LINCR1[INIT]) = 1.
Idle on Identifier Parity Error
0: Identifier Parity error does not reset LIN state machine.
1: Identifier Parity error reset LIN state machine.
This bit can be set/cleared in Initialization mode only (LINCR1[INIT]) = 1.
Wake-up Generation Request
Setting this bit generates a wake-up pulse. It is reset by hardware when the wake-up character has
been transmitted. The character sent is copied from DATA0 in BDRL buffer. Note that this bit cannot
be set in Sleep mode. Software has to exit Sleep mode before requesting a wake-up. Bit error is not
checked when transmitting the wake-up request.
Data Discard Request
Set by software to stop data reception if the frame does not concern the node. This bit is reset by
hardware once LINFlexD has moved to idle state. In Slave mode, this bit can be set only when HRF
bit in LINSR is set and identifier did not match any filter.
Data Transmission Request
Set by software in Slave mode to request the transmission of the LIN Data field stored in the Buffer
data register. This bit can be set only when HRF bit in LINSR is set.
Cleared by hardware when the request has been completed or aborted or on an error condition.
In Master mode, this bit is set by hardware when DIR bit in BIDR is set and header transmission is
completed.
27-42
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor