PXD20RM Datasheet, PDF (1336/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

1
1
1
Source clock / 128
NOTE:
The channel configuration registers are described for channel 3 -
CLKCH3(offset 0x000C) to RNCCH3 (offset 0x0030). The registers for the
other three channels are identical except that they have the offsets shown
below:
For channel 2, CLKCH2(offset 0x0034) to RNCCH2(offset 0x0058).
For channel 1, CLKCH1(offset 0x005C) to RNCCH1(offset 0x0080).
For channel 0, CLKCH0(offset 0x084) to RNCCH0(offset 0x00A8).
39.6.2.4 Clock Configuration Register for Channel 3 (CLKCH3)
The CLKCH3 register controls the clock for channel 3.
SGM Register Base + 0x000C (Channel 3)
SGM Register Base + 0x0034 (Channel 2)
SGM Register Base + 0x005C (Channel 1)
SGM Register Base + 0x0084 (Channel 0)
31
30
29
28
27
26
25
24
23
22
21
20
19
R
CLKS
W
0
0
0
0
0
0
0
0
0
0
0
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
15
R
W
Reset 0
14
13
12
11
10
9
8
7
6
5
4
3
PRSM
0
0
0
0
0
0
0
0
0
0
0
0
Figure 39-5. Clock Configuration Register for Channel 3 (CLKCH3)
18
17
16
PRSR
0
0
0
2
1
0
0
0
1
Field
31-30
CLKS
29-24
18-16
PRSR
15-0
PRSM
Table 39-8. CLKCH3 Register Description
Description
Clock Source Selection of Channel 3. See Table 39-6 for details.
Reserved.
Prescaler Range of Channel 3. These three bits determine the range of the prescaler clock, as shown in
Table 39-7
Prescaler Modulus Select. These 16 bits control the prescale modulus counter in the clock generator. The clock
divide ratio is (PRSM+1). A value of 0 disables the generated clock.
39.6.2.5 DDS Configuration Register for Channel 3 (DDSCH3)
DDSCH3 contains the accumulator increment value for Channel 3 DDS mode.
39-12
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor