PXD20RM Datasheet, PDF (280/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

If the current master is the highest priority master and it gives up the slave port by running an IDLE cycle
or by running a valid cycle to another location other than the slave port the next highest priority master
will gain control of the slave port. If the current access incurs any wait states then the transition will be
seamless and no bandwidth will be lost; however, if the current transaction is terminated without wait
states then one IDLE cycle will be forced onto the slave bus by the XBAR before the new master will be
able to take control of the slave port. If no other master is requesting the bus then IDLE cycles will be run
by the XBAR but no bandwidth will truly be lost since no master is making a request. Figure 9-9 illustrates
the effect of a higher priority master giving up control of the bus.
1
2
3
4
5
6
7
8
9
hclk
m0 request
m2 request
m4 request
Highest
Priority
Requester
Address/Cntrl
owner
htrans
Master 0
XBAR
Master 0
IDLE
NSEQ
Master 2 None Master 4
XBAR Master 2 XBAR
IDLE
NSEQ
IDLE
None
Master 4
NSEQ
XBAR
IDLE
hready
Figure 9-9. High to low priority mastership change
When the slave port is programmed for round-robin mode of arbitration then the slave port will switch
masters any time there is more than one master actively making a request to the slave port. This will
happen because any master other than the one which presently owns the bus will be considered to have
higher priority. Figure 9-10 shows an example of round-robin mode of operation.
9-22
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor