PXD20RM Datasheet, PDF (1183/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

31.6 Functional Description
Figure 31-1 shows the GFX2D top level block diagram.
31.6.1 Bus interface
The bus interface has a 32-bit AHB slave port and a 64-bit AXI master port.
31.6.2 Input unit
This unit handles the command stream input through the slave interface, status register reads, and external
interrupt generation with programmable interrupt handler. It connects to the slave port of the bus interface
unit where the CPU can feed in commands to the graphics processor.
31.6.3 Arbiter
The arbiter sits between the rendering core and the bus interface, handling prioritized arbitration of
memory reads and writes.
31.6.4 Burst cache
The burst cache handles the main memory traffic for the rendering pipeline. It is composed of 256-bit
blocks. The burst cache intrinsically works with pixel groups and caches recently used pixels. It also stops
pixels proceeding in the pixel pipeline, if the same memory location already has a pending write coming
from the pixel pipeline. This protection is done separately for the various 2D and VG buffers.
31.6.5 2D+VG unit
This unit handles all 2D-bitmap related operations. It has a rectangle rasterizer, which generates the source
and destination X and Y coordinates. The rasterizer can also operate in right-to-left and/or bottom-to-top
direction.
Raster operation (ROP) is supported between the source, pattern/mask and destination data. The data is
then written to the destination bitmap. Separate ROPs can be used for masked and unmasked pixels
(ROP4). The color can also be alpha blended with the destination with either per pixel or constant alpha
value.
This unit also contains a vector graphics rasterizer, which is capable of rasterizing anti-aliased complex
polygons.
31.6.6 2D+VG unit level architecture
Figure 31-13 shows the architecture of the 2D+VG unit.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
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