PXD20RM Datasheet, PDF (1009/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Offset: 0x9C
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 27-42. DMA Rx enable register (DMARXE)
Table 27-41. DMARXE field descriptions
Field
DREn
DMA Rx channel n enable
0 DMA Rx channel n disabled
1 DMA Rx channel n enabled
Description
Note: When DMARXE = 0x0, the DMA Rx interface FSM is forced (soft reset) into the IDLE state.
27.11 DMA interface
The LINFlexD DMA interface offers a parametric and programmable solution with the following features:
• LIN Master node, TX mode: single DMA channel
• LIN Master node, RX mode: single DMA channel
• LIN Slave node, TX mode: 1 to N DMA channels where N = max number of ID filters
• LIN Slave node, RX mode: 1 to N DMA channels where N = max number of ID filters
• UART node, TX mode: single DMA channel
• UART node, RX mode: single DMA channel + timeout
The LINFlexD controller interacts with an enhanced direct memory access (eDMA) controller; see the
description of that controller for details on its operation and the transfer control descriptors (TCDs)
referenced in this section.
27.11.1 Master node, TX mode
On a master node in TX mode, the DMA interface requires a single TX channel. Each TCD controls a
single frame, except for the extended frames (multiple TCDs). The memory map associated with the TCD
chain (RAM area and LINFlexD registers) is shown in Figure 27-43.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
27-53