PXD20RM Datasheet, PDF (529/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

PCLK
pixel
data
invalid data
1
2
34
DELTA_X
1
invalid data
HSYNC
Data
Enable
(DE)
PW_H
BP_H
DELTA_X
FP_H
DELTA_X is the horizontal resolution of the display
HSYNC
line
data
invalid data
1
2
34
DELTA_Y
invalid data
VSYNC
Data
Enable
(DE)
PW_V
BP_V
FP_V
1/RR where RR is the frame refresh rate
Figure 12-62. HSYNC and VSYNC timing diagram
The number of pixel data slots in the horizontal timing diagram is defined by the width of the panel. The
number of line data slots is defined by the height of the panel. Both of these values are defined in the
DISP_SIZE register (DELTA_X, DELTA_Y). The width of the panel must always be defined as a multiple
of 16.
The timing of the pixel clock is defined by the DIV_RATIO register and the frequency of the clock
supplied to the DCULite.
In addition to defining the number and timing of pixels in each line and the number of lines, it is normal
for TFT LCD panel manufacturers to define other timing signals in terms of pixel clock periods or of the
number of horizontal lines. The DCULite also follows this convention.
If the TFT LCD panel requires a horizontal synchronizing signal (HSYNC) and/or a data enable signal,
then these can be configured using the fields in the HSYN_PARA register. HSYNC provides a pulse to
give the panel notice that the next line of pixel data is about to start, and the data enable signal indicates
when that data is present. The PW_H bit field indicates the width of the HSYNC pulse, in pixel data clock
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
12-67