PXD20RM Datasheet, PDF (728/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

input input
filter
MODE
register
MODE
decoder
mode 0
logic
mode 1
logic
mode n
logic
uc_ctrl
global counter bus[A]
local counter bus
[C/D]
BSL[0]
internal counter
CNT
BSL[1]+logic
A2
BSL[1]+logic
General
Purpose
Registers
==
A Comparator
A1
uc_datapath
B2
BSL[1]+logic
B1
B Comparator
==
Figure 18-16. Unified Channel Control and Datapath Block Diagrams
18.7.1.1 UC Modes of Operation
The mode of operation of the Unified Channel is determined by the mode select bits MODE[0:6] in the
CCR[n] (see Figure 18-17 for details).
When entering an output mode (except for GPIO mode), the output flip-flop is set to disabled state
according to ODIS bit in the CCR[n].
As the internal counter CCNTR[n] continues to run in all modes (except for GPIO mode), it is possible to
use this as a time base if the resource is not used in the current mode.
In order to provide smooth waveform generation even if A and B registers are changed on the fly, in the
MCB, OPWFMB, and OPWMB the A and B registers are double buffered.
18-26
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor