PXD20RM Datasheet, PDF (1610/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 50-6. Performance optimization checklist—Part 2. Software configuration
Description
Registers
Details
Compiler optimization
—
Use the features of the compiler to select the
optimum trade off between code size and
performance improvements.
Hardware Single Precision
Floating Point
Enable with MSR[SPE]
Set compiler switches to specify using hardware
single precision floating point as opposed to
software emulation.
Signal Processing Extensions Enable with MSR[SPE]
Take advantage of the SPE-APU to encode time
critical functions using SPE assembly code.
Variable Length Encoding
Enabled with TLB_MAS2[VLE] Set compiler switches and configure the MMU to
take advantage of the VLE-APU.
Table 50-7. Performance optimization checklist—Part 3. Peripherals and general application guidelines
Peripherals and general application guidelines
Use eDMA rather than the core to move data where possible. Most peripherals can generate eDMA requests to shift
data.
• Use DMA to fill and empty communication devices buffers.
• Use DMA to copy graphics from flash into RAM for further processing or reuse
• Use DMA to initialize DCU and DCULite CLUT
Shift loading from the CPU to the e200z0h and CTU whenever possible.
• The e200z0h can handle interrupts and scheduling for comunications peripherals.
• The CTU can trigger the ADC directly with no need for CPU interruption.
Avoid software polling and allow peripherals to trigger interrupts or request eDMA servicing.
• Use hardware instead of software vectored interrupts to reduce latency.
• Trigger eDMA requests rather than interrupting the CPU to move data/results.
50-12
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor