PXD20RM Datasheet, PDF (265/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

MPRn
Master Priority Register n
Addr
$BASE + 0x000 + n*100
Wait State: 0
Access: S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MSTR_7
MSTR_6
MSTR_5
MSTR_4
TYPE: r rw rw rw r rw rw rw r rw rw rw r rw rw rw
Reset: 0 0 0 0 0 1 1 0 0 1 0 1 0 1 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
MSTR_3
MSTR_2
MSTR_1
MSTR_0
TYPE: r rw rw rw r rw rw rw r rw rw rw r rw rw rw
RESET: 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0
Note: for n = 0 to 7
Figure 9-3. Master Priority Register n
Name
Bit 0
MSTR_7
Table 9-5. Master Priority Register Descriptions
Description
Settings
Master Priority Register Reserved - This bit is reserved NA
for future expansion. It is read as zero and should be
written with zero for upward compatibility.
Master 7 Priority - These bits set the arbitration priority 000This master has the highest priority
for master port 7 on the associated slave port.
when accessing the slave port.
Bit 4
MSTR_6
These bits are initialized by hardware reset.
The reset value is 111
111This master has the lowest priority
when accessing the slave port.
Master Priority Register Reserved - This bit is reserved NA
for future expansion. It is read as zero and should be
written with zero for upward compatibility.
Master 6 Priority - These bits set the arbitration priority 000This master has the highest priority
for master port 6 on the associated slave port.
when accessing the slave port.
Bit 8
MSTR_5
These bits are initialized by hardware reset.
The reset value is 110
111This master has the lowest priority
when accessing the slave port.
Master Priority Register Reserved - This bit is reserved NA
for future expansion. It is read as zero and should be
written with zero for upward compatibility.
Master 5 Priority - These bits set the arbitration priority 000This master has the highest priority
for master port 5 on the associated slave port.
when accessing the slave port.
Bit 12
These bits are initialized by hardware reset.
The reset value is 101
111This master has the lowest priority
when accessing the slave port.
Master Priority Register Reserved - This bit is reserved NA
for future expansion. It is read as zero and should be
written with zero for upward compatibility.
PXD20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
9-7
Preliminary—Subject to Change Without Notice