PXD20RM Datasheet, PDF (1372/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Source State
ATTK
ATTK
SUST
SUST
RELS
RELS
RELS
NOPT
NOPT
Table 39-41. DDS mode State Machine (continued)
Destination State
IDLE/STOP
SUST
IDLE/STOP
RELS
IDLE/STOP
NOP
ATTK
IDLE/STOP
ATTK
Transfer
Condition
Description
B
The generation of the sound can be stopped
by deasserting the SOG anytime.
C
If the ASR envelope reach the target volume of
Attack phase, Sustain phase will be entered.
D
The generation of the sound can be stopped
by deasserting the SOG anytime.
E
When the target sustain timing is reached, the
Release phase will be entered.
F
The generation of the sound can be stopped
by deasserting the SOG anytime.Or if the
no-output phase is disabled, the note pulse
count is enabled and the target note pulse
number is reached, the IDLE phase will be
entered.
G
If the ASR envelope reach the target volume of
Release phase and the no-output phase is
enabled, the no-output phase will be entered.
H
If the ASR envelope reach the target volume of
Release phase and the no-output phase is
disabled, the no-output phase will be entered.
I
The generation of the sound can be stopped
by deasserting the SOG anytime.
Or when the target note pulse number is
reached (if the target note pulse count is
enabled), the generation ends.
J
When the target no-output timing is reached,
the Attack phase will be entered if the target
note pulse number isn’t reached or disabled.
39.7.3 SGM architecture
The SGM consists of a clock configuration logic, IPS Interface, four identical sound channels, a
re-sampling block, mixer with volume control, PWM output and I2S interface. Refer to for a block
diagram of the SGM. The following sections discuss each in turn.
39.7.4 SGM clocking
The SGM uses the following clocks:
Source clocks:
• System clock
• SGM module clock (maximum frequency half the system clock)
39-48
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor